Embedded & VLSI

Our expertise ranges across various processor families and hardware platforms, such as:

• Processor Families: ARM, ADSP, TI OMAP, TI DaVinci, MIPS and FreeScaleiMX Series
• GUI Development: Qt, OpenGL, OpenVG, MiniGUI and Android GUI framework

RTOS and Mobile Hardware: VxWorks, QNX, BMP, ucLinux, RTX, uCOS III and Android Our projects involved development based on hardware target platforms involving Beagle, DaVinci Processors, FreeScaleSabreLite and Atheros Wireless System on Chips. We are currently providing development and Testing Services in LSP (Linux support Packages), BSP (Board Support Packages) and applications supporting Digital Video Mirrors, DVRs and other Embedded Multimedia products. We also develop Qt Applications targeted at Embedded Products.

VLSI

Kapital Infotech Technologies has different engagement models, from consulting to Final delivery of chips. We provide consulting services in all ASIC Design domains.

Kapital Infotech Technologies team expertise in Design Implementation encompasses flows/methodologies from front-end to the back-end. The core-skills include RTL Design, Verification, RTL Synthesis, Timing Analysis, DFT, Formal Verification, Physical Design Closure (Floor planning, Clock Tree Synthesis, P&R, Timing, Noise, Power & IR-Drop/Electro migration Analysis and Physical Verification).

The services in Design Implementation encompass complete RTL to GDSII implementation in Synopsys & Cadence flows in 32nm, 45nm, 65nm, 90nm, 130nm.

Kapital Infotech Technologies has credentials in working on Physical Design expertise across complex blocks and has experience with timing closure on flat as well as hierarchical designs.

We have a successfully executed turn key projects - Spec to Tested Chips, Consultation services we have right from RTL design to Finished chips. We have good relations with multiple Semiconductor fabs, can give you cost effective solution.

Design:

• Architectural Design Implementation
• Spec Development RTL, Implementation (SV, Verilog, VHDL,) & Simulation.
• Synthesis
• Timing
• Verification

Verification:

• Chip and System level verification
• Verification flow and Methodologies
• Set up Verification environment, Test benches and Test Plan